LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bascule_D IS
PORT (d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END bascule_D;
ARCHITECTURE comportement OF bascule_D IS
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
q <= '0';
ELSIF (clk'EVENT AND clk='1') THEN
q <= d;
END IF;
END PROCESS;
END comportement;
library ieee;
use ieee.std_logic_1164.all;
entity Bascule is
port(J,K,Clk,Set, Reset : in std_logic;
Q, Q_bar : out std_logic);
end Bascule;
architecture bascule_JK of Bascule is
signal SIG : std_logic;
signal JK : std_logic_vector (1 downto 0);
begin
JK(1) <= J;
JK(0) <= K;
process(Clk, Set, Reset)
begin
if (Reset = '0'and Set = '0') then
SIG <= '0';
elsif (Reset = '0' and Set = '1') then
Sig <= '0';
elsif (Reset ='1' and Set ='0') then
Sig <='1';
elsif (Reset = '1' and Set ='1') then
if (Clk'event and Clk ='0') then
case JK is
when "00" => SIG <= SIG;
when "01" => SIG <= '0';
when "10" => SIG <= '1';
when "11" => SIG <= not SIG;
when others => SIG <= '-';
end case;
else
SIG <= SIG;
end if;
end if;
end process;
Q <= SIG;
Q_bar <= not SIG;
end bascule_JK;